上图来自techlevated finfet vs mosfet planar transistor。在stackexchange question about the basic differences between a mosfet and a fet，有人回答：
A MOSFET is a type of FET. It stands for "Metal Oxide Semiconductor Field Effect Transistor". All MOSFETs are FETs, not all FETs are MOSFETs. But the term is so common that things that are not actually MOSFETs are still called "MOSFETs", so there isn't really much difference; the terms are kind of interchangeable.
综上，CPU用的也算CMOS。据nutsvolts understanding digital logic ics part，In 1972, practical CMOS arrived...the '4000'-series. This new family was not as fast as the TTL then in use in the rival '74'-series, but in the mid 1980s, a new high-speed type of CMOS was developed and introduced as a new member of the 74 family of devices. The advantages of this new 'fast' CMOS were so great that in 1994, it overtook TTL in popularity within the 74-series, finally making CMOS the most popular of all modern digital IC technologies.
The MC74AC374/74ACT374 is a high−speed, low−power octal D-type flip-flop:
AC是芯片的名字
据Comprehensive Design and Timing Analysis for High speed Master Slave D Flip-Flops using 18 nm FinFET Technology，Implementation of D Flip-Flop design, suitable test circuit and timing analysis is performed on the Cadence virtuoso analog design environment tool. Using appropriate excitations, parametric analysis is carried out to obtain the setup and hold time values for various designs of D Flip-Flop including the proposed design. From the results, it was observed that the setup time and hold time varied with different clock edge rates. For the edge rates of 0.01, 0.05, and 0.1 ns, it was observed that the proposed design gave setup times of 54.9, 61.2, and 69.8 ps and hold times of −30.7, −43.6 and, −48.8 ps respectively.
总之，我看的书太老了，还以为要十几到几十纳秒。
据Performance Comparisons between 7nm FinFET and Conventional Bulk CMOS Standard Cell Libraries, Qing Xie, Xue Lin, Yanzhi Wang, Shuang Chen, Mohammad Javad Dousti, Massoud Pedram，[西人IGBT玩腻了，改玩LGBT了？]，
据icdesigntips setup and hold time explained，Setup time is the required time duration that the input data MUST be stable before the triggering-edge of the clock. How do EDA tools know the setup time requirement for each flip-flop in the standard cells? The answer is the timing library. It always comes with the PDK (Process Design Kit). In case that you design your own flip-flop circuit, you need to characterize the timing of the Flip-Flop and provide this timing library during the chip implementation. The tools used for timing characterization are Liberate for Cadence EDA or SiliconSmart for Synopsys EDA. Below is an example of setup time in the timing library. Basically, it is a lookup table to provide different setup time based on input and clock transitions.
单位是啥呢？ns的可能性很大
据Significance of negative setup and hold time - Electrical Engineering Stack Exchange，setup和hold韶光可以是负数。
Liberty是Liberate拼错了吗？不，Liberty是Synopsys的。我真讨厌这帮人啊！
Liberty Reference Manual能搜到不少。
DC Electrical Characteristics for AC, AC Electrical Characteristics for AC，AC Electrical Characteristics for ACT搜不到啊——噢~~~ The AC00/ACT00 contains four, 2-input NAND gates，AC和ACT是芯片的名字：74AC00, 74ACT00 Quad 2-Input NAND Gate。
